The present invention relates to a device for controlling access from a plurality of masters to a shared memory composed of a plurality of banks each having a plurality of pages, and more particularly, to a technique for enhancing the efficiency of data transfer.
Some system LSIs are known to adopt a configuration called unified memory architecture in which a plurality of masters such as a processor and a hardware engine access a shared memory. As such a memory, a synchronous dynamic random access memory (SDRAM) or the like is known. An SDRAM is composed of a plurality of banks, each of which is composed of a plurality of pages. To access an SDRAM, it is necessary to first activate a page and then issue an access command after a lapse of a fixed time. Moreover, in accessing a different page of the same bank, processing called precharge must be made for the bank to be accessed, and thereafter the bank to be accessed must be newly activated. In SDRAM access, therefore, when different pages of the same bank are accessed in succession, a page mishit may occur, degrading the access efficiency. On the other hand, access to one bank is allowed even when precharge and activation are underway for another bank. Hence, if only arrangement can be made so that different banks are accessed in succession, the SDRAM access efficiency will be enhanced. In SDRAM, also, the access efficiency degrades at the time of switching between read access and write access and the time of refresh required every fixed time period.
As methods for enhancing the SDRAM efficiency considering the natures described above, the following techniques are disclosed, for example.
In Japanese Laid-Open Patent Publication No. 2001-356961 (Patent Document 1), disclosed is a technique in which, examining information on the banks to be accessed by commands sent from a plurality of masters and on whether the access is read or write and considering the state of the SDRAM in arbitration among the masters, access is selected so that page mishits and read/write switching less occur.
In the above technique, however, a command sent from one master is limited to access to one bank. Hence, even when the master desires transfer over a plurality of bank regions, the issuance order of commands is not necessarily the order in which efficient memory access is ensured because the command issuance order is determined depending on the operation of the master.
To solve the above problem, Japanese Laid-Open Patent Publication No. 2004-310394 (Patent Document 2) discloses a technique in which commands sent from masters are accepted bank by bank and arbitration among banks is made so as to reduce page mishits.
Japanese Laid-Open Patent Publication No. 2002-268942 (Patent Document 3) discloses a technique in which when a master issues a command for access over a plurality of banks, the command is divided into micro-commands for the banks to be accessed, after arbitration among masters. The micro-commands are then put in queues for the respective banks and managed.
Japanese Laid-Open Patent Publication No. 2006-260472 (Patent Document 4) discloses a technique in which a command for access over a plurality of banks issued by a master is divided into commands for the banks, and such commands are sorted in an order in which page mishits can be reduced, to thereby improve the memory access efficiency.
Patent Documents 3 and 4 above also refer to a method of using address mapping called interleave in which banks are switched every small memory unit so that a command issued by a master is for access over a plurality of banks.
In the processing high in real-time property such as moving picture processing and the processing by a processor and the like whose latency directly affects the performance, high-speed response is required depending on the degree of emergency. Hence, in addition to enhancing the memory access efficiency, shortening the latency is also required for an access high in the degree of emergency.
In the technique disclosed in Patent Document 2, commands using the same bank are selected sequentially in arbitration among masters, and this may degrade the efficiency.
The efficiency may be improved by increasing the number of accepted commands per bank. In this case, however, when an access with high priority occurs, this access must wait until the large number of commands already accepted have been processed even if high priority is given to this access in the arbitration among masters. This will increase the latency.
In the techniques disclosed in Patent Documents 3 and 4, efficient access will be attained as long as commands of masters are all for access over a plurality of banks. However, since some masters such as a processor perform random access within a small size, it is unlikely to have access over a plurality of banks for all commands.
In the technique disclosed in Patent Document 4, as a result of arbitration of accesses from a plurality of masters, such accesses may continue in succession. When such accesses are to the same bank, a page mishit may inevitably occur.
In the technique disclosed in Patent Document 3, the possibility of accepting commands free from page mishit can be increased by increasing the number of stages in the queue for each bank. In this case, however, the problem of increasing the latency of a command with high priority may occur as in Patent Document 2 above.
Also, even though the bank switching unit is made extremely small to ensure that all commands are for access over a plurality of banks, no effect will be obtained because, with such a small access unit, the access interval caused by a page mishit can not be concealed with access to another bank.
As described above, in a system having a variety of performance requirements and memory access sizes, the conventional techniques have respective problems to overcome to enhance the response performance for the processing high in the degree of emergency and the memory access efficiency.